Development of a software simulator of networks on a chip
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Abstract
The article presents the concept of networks-on-chip (NoC) as a promising alternative to communication subsystem for multiprocessor systems with bus architecture. The networks simulator developed as a necessary software tool to evaluate NoC performance parameters. Its possibilities are considered and the results of its approbation are given
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References
L. T. Canham, “Silicon Quantum Wire Array Fabrication by Electrochemical and Chemical Dissolution of Wafers,” Applied Physics Letters, vol. 57, no. 10, 1990, p. 1046. doi:10.1063/1.103561
Korsunskaya N.E., Stara T.R., Homenkova L.YU., Svezhencova E.V., Mel'nichenko N.N., Sizov F.F., “Priroda izlucheniya poristogo kremniya, poluchennogo himicheskim travlenim [The nature of radiation from porous silicon obtained by chemical etching]“, Fіzika i tekhnika poluprovodnikov, vol. 44, no. 1, pp. 82 – 86, 2010
