Method of Parametrical Optimization of Multi-Core Processors
Main Article Content
Abstract
A post-layout design power optimization algorithm is suggested. Both, gate sizing and
multi threshold optimization methods are implemented. The main advantages are the improved performance characteristics and intactness of the initial design placement and routing. Free layout spaces due to decrease of optimized cell sizes is suggested to be filled with
decoupling capacitors which decreases power
supply noises. The algorithm ensures decrease
of static and dynamic power by respectably
19% and 11% for eight-core OpenSPARC processor architectures. It demonstrates improved
optimization time compared to existing algorithms by about 29%, in expense of decrease of
optimized power by 2-5%
Article Details
This work is licensed under a Creative Commons Attribution 4.0 International License.
Authors who publish with this journal agree to the following terms:- Authors retain copyright and grant the journal right of first publication with the work simultaneously licensed under a Creative Commons Attribution License that allows others to share the work with an acknowledgement of the work's authorship and initial publication in this journal.
- Authors are able to enter into separate, additional contractual arrangements for the non-exclusive distribution of the journal's published version of the work (e.g., post it to an institutional repository or publish it in a book), with an acknowledgement of its initial publication in this journal.
- Authors are permitted and encouraged to post their work online (e.g., in institutional repositories or on their website) prior to and during the submission process, as it can lead to productive exchanges, as well as earlier and greater citation of published work (See The Effect of Open Access).
References
K. Michael and F. David, Low Power Methodology Manual for System-on-Chip Design, Springer, 2007.
B. Swarup and M. Saibal, Low-Power Variation Tolerant Design in Nanometer Silicon, Springer, 2011, p. 456.
C. Kyu-won and C. Abhijit, “UDSM (UItra-Deep SubMicron)-Aware Post-Layout Power Optimization for Ultra Low-Power CMOS VLSl”, ISLPED’03, pp. 72–77, 2003.
M. Ketkar and S. S. Sapatnekar, “Standby power optimization via transistor sizing and dual threshold voltage assignment”, in Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design - ICCAD ’02, San Jose, California, 2002, pp. 375–378. DOI:10.1145/774572.774628
K. Ken, Power Supply Noise Reduction, 2004. www.designers-guide.org
Design Compiler User Guide, 2010, p. 399.
IC Compiler User Guide, 2010, p. 100.
Y. Liu and J. Hu, “A new algorithm for simultaneous gate sizing and threshold voltage assignment”, in Proceedings of the 2009 international symposium on Physical design - ISPD ’09, San Diego, California, USA, 2009, p. 27. DOI:10.1145/1514932.1514940
