Statistical analysis of time delays multiprocessor systems
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Abstract
In this paper a method of statistical static timing analysis (SSTA) for multicore processors is proposed. An effective method of timing analysis based on simultaneous application of usual static as well as statistical static timing analysis. At the first stage usual static timing analysis (STA) is applied and at the second stage - SSTA. The proposed method of analysis allows reaching of acceptable analysis results from the practical viewpoint of accuracy at considerably small expenses of machine runtime
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References
D. Blaauw, K. Chopra, A. Srivastava, and L. Scheffer, “Statistical Timing Analysis: From Basic Principles to State of the Art”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 4, pp. 589–607, Apr. 2008 DOI:10.1109/TCAD.2007.907047
V. Veetil, D. Sylvester, and D. Blaauw, “Efficient Monte Carlo based incremental statistical timing analysis”, in Proceedings of the 45th annual Design Automation Conference, Anaheim California, 2008, pp. 676–681. DOI:10.1145/1391469.1391645
S. V. Kumar, C. V. Kashyap, and S. S. Sapatnekar, “A framework for block-based timing sensitivity analysis”, in Proceedings of the 45th annual Design Automation Conference, Anaheim California, 2008, pp. 688–693. DOI:10.1145/1391469.1391647
Design Compiler User Guide, Synopsys Inc., 2008
PrimeTime User Guide, Synopsys Inc., 2008
PrimeTime-VX User Guide, Synopsys Inc., 2009
A. Nardi, “Use of Statistical Timing Analysis on Real Designs”, in 2007 Design, Automation & Test in Europe Conference & Exhibition, Nice, France, 2007, pp. 1–6. DOI:10.1109/DATE.2007.364531
