A parallel algorithm for reducing the dimension of RLC circuits
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Abstract
Parallel implementation of the RLC-circuit reduction algorithm based on Y-Δ transformation using modified cluster Sangiovanni – Vincentelli algorithm for tearing graphs was proposed. Results of modeling that prove efficiency of the proposed algorithm are presented.
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References
A. Petrenko, “Network package forcomputer design of microelectromechanical systems”, Developmentinformation and telecommunicationstechnologies and development of information society in Ukraine, pp. 143–156, 2007.
V. V. Ladogubets, A. Y. Beznosyk, A. V. Kramar, and A. D. Finogenov, “MEMS macromodeling methods”, Electronics and communication, no. 1-2, pp. 244–248, 2008.
B. Sheehan, “TICER: Realizable reduction of extracted RC circuits”, in 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051), San Jose, CA, USA, 1999, pp. 200–203. DOI: 10.1109/ICCAD.1999.810649
C. Amin, M. Chowdhury, and Y. Ismail, “Realizable RLCK circuit crunching”, in Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451), Anaheim, CA, USA, 2003, pp. 226–231. DOI: 10.1109/DAC.2003.1218969
Ladogubets V.V., Rudenko Yu.A., Ladogubets A.V., “Reduction algorithmdimensions of RLC circuits”, Electronicsand communication, vol. 21, pp. 72–74, 2004.
A. Sangiovanni-Vincentelli and L. Chua, “An efficient heuristic cluster algorithm for tearing large-scale networks”, IEEE Transactions on Circuits and Systems, vol. 24, no. 12, pp. 709–717, Dec. 1977. DOI:10.1109/TCS.1977.1084298
A. I. Petrenko, V. V. Ladogubets, A. Y. Beznosik, A. D. Finogenov, and A. V. Chkalov, “Calculation of natural frequencies membrane structures using circuit design packages”, Radio electronics: News of universities, no. 7, pp. 19–25, 2009.
