Linear placement of digital integrated circuit cells taking into account delay reserves in circuits
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Abstract
A method of linear placement of standard cells of digital integrated circuits (IC), based on the preliminary timing analysis of the circuit and definition of linear co-ordinates corresponding to bottom and top boundaries of signal delay in nets. Definition of preliminary linear coordinates of cells placement is made on the average value of distance from linear co-ordinates of the bottom boundaries of a signal delay of incidental nets to the corresponding cell. Reserves of time of corresponding nets considered as a weight. Final placement of cells is made by linear moving of cells co-ordinates before elimination of cells is overlappings
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